A multilevel cell memory is comprised of multilevel cells, each of which is able to store multiple charge states, or levels. Each of the charge states is associated with a memory element bit pattern.
FIG. 1 shows a representation of a prior art multilevel cell that stores four charge states: Levels 0-3. Level 3 maintains a higher charge than level 2; level 2 maintains a higher charge than level 1; level 1 maintains a higher charge than level 0. A reference voltage separates the various charge states. Vref2 separates level 3 and level 2. Vref1 separates level 2 and level 1. Vref0 separates level 1 and level 0.
Each charge state has an associated memory element bit pattern. For one implementation, the memory element bit pattern `00` is associated with level 3, the memory element bit pattern `10` is associated with level 2, the memory element bit pattern `01` is associated with level 1, and the memory element bit pattern `11` is associated with level 0.
A multilevel cell memory is able to store more than one bit of data based upon the number of charge states that it can store. For example, a multilevel cell memory that can store four charge states can store two bits of data; a multilevel cell memory that can store eight charge states can store three bits of data; a multilevel cell memory that can store sixteen charge states can store four bits of data. For each of the n-bit multilevel cell memories, various memory element bit patterns can be implemented to be associated with each of the different charge states.
The number of charge states storable in a multilevel cell, however, is not limited to powers of two. For example, a multilevel cell with three charge states stores 1.5 bits of data. When this multilevel cell is combined with additional decoding logic and coupled to a second similar multilevel cell, three bits of data are provided as output of the two-cell combination. Various other multi-cell combinations are also possible.
One example of a multilevel cell memory is described in U.S. Pat. No. 5,450,363, entitled "Gray Coding for a Multilevel Cell Memory System," by Christopherson et al., and issued to the common assignee of this application. The '363 patent describes one implementation of a multilevel cell memory. Multilevel cell memories can be used in Dynamic Random Access Memory (DRAM) and various types of Read-Only Memory (ROM), such as an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), and flash Erasable Programmable Read-Only Memory (flash EPROM).
FIG. 2 shows a prior art representation of a processor 100 and multilevel cell memory 104. A processor 100 is coupled to a bus 102 and the memory 104. The memory 104 contains an interface controller 105 and a multilevel cell memory array 150. The processor 100 is coupled via the bus 102 to the interface controller 105. The processor 100 is also coupled via the bus 102 to the multilevel cell memory array 150. The interface controller 105 provides the necessary operations to control the multilevel cell memory array 150. For one embodiment, the interface controller 105 and multilevel cell memory array 150 are located on a single integrated circuit die.